A) Field of the Invention
The present invention relates to a semiconductor device manufacturing method and a reticle pattern forming method, and more particularly to a semiconductor device manufacturing method including an oblique ion implantation process and a method of forming reticle patterns to be used by the manufacturing method.
B) Description of the Related Art
FIG. 18A is a plan view of a static random access memory (SRAM), and FIG. 18B is a cross sectional view taken along one-dot chain line B18-B18 shown in FIG. 18A. A p-type well 215 and a p-type well 217 extending in a vertical direction in FIG. 18A are disposed in parallel to each other. An n-type well 216 is disposed between the p-type wells. A border between the n- and p-type wells is indicated by a broken line. One memory cell 210 having six MOS transistors extends from the inside of the p-type well 215 to the inside of the p-type well 217 passing across the n-type well region 216. A PMOS active region 211 is defined in the n-type well 216 and NMOS active regions 212 and 213 are defined in the p-type well 217.
One NMOS transistor T1 constituting a portion of the memory cell 210 is disposed in the NMOS active region 212 and another PMOS transistor T2 constituting a portion of the memory cell 210 is disposed in the PMOS active region 211. One gate pattern 205 intersecting both the PMOS active region 211 and NMOS active region 212 constitutes a gate pattern of the NMOS transistor T1 and PMOS transistor T2. Another gate pattern 206 intersects the PMOS active region 213.
When pocket implantation for the NMOS transistor T1 is to be performed, the PMOS active region 211 is covered with a resist pattern 220. Pocket implantation, also called halo implantation, means ion implantation for implanting impurity ions of a conductivity type opposite to that of source/drain regions into a region between the source region and channel region and a region between the drain region and channel region, deeper than the source/drain regions at a low impurity concentration, in order to suppress the short channel effect of MOS transistors. Impurity doped regions formed by pocket implantation are called pocket regions. Pocket implantation is also called halo implantation.
Pocket implantation is usually performed along oblique directions to make impurities sink into a region under the gate pattern. For example, ion implantation is performed along four directions in total: two directions tilting a virtual straight line perpendicular to the substrate surface in directions parallel to the direction (hereinafter simply called a “gate pattern direction”) along which the gate pattern traverses the active region; and two directions tilting the virtual straight line in directions perpendicular to the gate pattern direction. Ion implantation is performed in some cases by rotating the substrate by 360°.
FIG. 18B shows ion implantation along a direction 230 tilting the virtual straight line perpendicular to the substrate surface from the side of the NMOS active region 212 toward the side of the PMOS active region 211. In this case, the PMOS active region 211 is covered with a resist pattern 220. As a space between the NMOS active region 212 and PMOS active region 211 becomes narrow, a portion of the NMOS active region 212 is shaded by the resist pattern 220. Impurity ions do not reach the shaded portion. An impurity concentration of the pocket region in the shaded portion is therefore lower than that in other portions.
A channel is likely to be generated in a low impurity concentration portion of the pocket region, more than a central portion of the active region. A desired threshold voltage cannot be obtained in some cases. A size of the shaded portion of the resist pattern 220 varies depending upon variations in the position and shape of the resist pattern 220. The characteristics of MOS transistors have therefore variations.
JP-A-HEI-8-279612 discloses pocket implantation techniques along two directions tilting toward a direction perpendicular to the gate pattern direction. If this pocket implantation along these two directions is performed, the NMOS active region 212 shown in FIG. 18B is not shaded by the resist pattern 220. It is therefore possible to suppress variations in the characteristics of the transistor T1.